As the size of devices in semiconductor chips is reduced without a corresponding reduction in voltage, channel hot carrier effect becomes one of the most significant limitations For deep sub-micron metal oxide semiconductor (MOS) transistors. This effect is caused by a high electric field near the drain junction resulting From the short channel length and the high supply voltage. This effect is more serious For an n-channel MOS transistor than For a p-channel MOS transistor because the impact ionization rate of an electron is higher than that of a hole, i.e., more electron-hole pairs are generated by an electron than by a hole. Further, electrons gain sufficient energy and become "hot" under the high electric field. Those hot electrons can inject into the gate oxide, resulting in a gate current. They can also cause impact ionization near the drain and generate a current into the substrate.
To mitigate the channel hot carrier effect, the lightly-doped drain (LDD) structure has been proposed. In the LDD structure, a lightly-doped buffer zone between an n.sup.+ heavily-doped drain and the gate is used to dilute the high electric field near the drain junction. The LDD structure is typically formed by implanting a low energy (40 KeV) phosphorous dopant at a dose of 5.about.30.times.10.sup.12 ions/cm.sup.2 to form an n.sup.- region after the polysilicon gate is Formed. Then, an oxide is chemical vapor deposited and thereafter etched to form spacers on the sidewalls of the gate. The spacers then serve as a mask for a heavy arsenic implant to form n.sup.+ regions.
Unfortunately, the location of the peak electric field in a LDD structure may shift so that negative charges are generated in the oxide above the n.sup.- region, resulting in increased series resistance in n.sup.- region. Thus, a small drain-to-gate overlap should be provided to ensure the location of the peak electric field stays underneath the gate electrode.
Another technique to overcome the series resistance problem, known as self-aligned silicide (salicide) technology, has been proposed. This process combines the best features of a polysilicon gate with self-alignment. In salicide technology, a gate sidewall oxide is formed which protects the gate sidewall form shorting to the source/drain regions after silicidation. The gate sidewall oxide is formed either by depositing and anisotropically etching a chemical vapor deposited oxide layer or by selective oxidation of sidewalls of the gate on which there is a silicon nitride layer. See p. 222, of C. M. Osburn et al., "High Conductivity Diffusions and Gate Regions Using Self-Aligned Silicide Technology," Electrochemical Society Proceedings, First International Symposium VLSI Science and Technology, Vol. 82-7, 1982.
During the silicidation process, some by-product impurities such as the F atom in forming tungsten silicide, will diffuse into the gate oxide, resulting in a thicker gate oxide. The thicker the gate oxide, the slower the device and the higher threshold voltage. See pp. 623-625, of S. L. Hsu et al., "Direct evidence of gate oxide thickness increase in tungsten polycide processes," IEEE Electron Device Letter, Vol. EDL-12, 1991. Moreover, the resistance between poly gate and silicide is large owing to the rough surface of the polysilicon. See pp. 176-179, of H. Yen, "Thermal treatment and under layer effects on silane and dichlorosilane based tungsten silicide for deep submicron interconnection processes," VLSI Technology, system, and, Applications, 1995. An improved poly gate using stacked-amorphous-silicon has been proposed. The stacked-amorphous-silicon is used in this technology to provide a smoother gate surface to reduce the resistance mentioned above, and provide a structure that is harder for the F atom to penetrate into gate oxide. See pp. 1797-1803, of S. L. Wu et al., "Characteristics of polysilicon contacted shallow junction diode formed with a stacked-amorphous-silicon film," IEEE Electron Devices, vol. ED-40, 1993.